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92 lines
1.8 KiB
Python
92 lines
1.8 KiB
Python
from random import randrange
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from myhdl import *
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ACTIVE_LOW, INACTIVE_HIGH = 0, 1
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def Inc(count, enable, clock, reset):
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""" Incrementer with enable.
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count -- output
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enable -- control input, increment when 1
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clock -- clock input
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reset -- asynchronous reset input
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n -- counter max value
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"""
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@always_seq(clock.posedge, reset=reset)
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def incLogic():
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if enable:
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count.next = count + 1
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return incLogic
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def testbench():
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m = 3
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count = Signal(modbv(0)[m:])
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enable = Signal(bool(0))
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clock = Signal(bool(0))
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reset = ResetSignal(0, active=0, async=True)
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inc_1 = Inc(count, enable, clock, reset)
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HALF_PERIOD = delay(10)
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@always(HALF_PERIOD)
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def clockGen():
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clock.next = not clock
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@instance
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def stimulus():
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reset.next = ACTIVE_LOW
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yield clock.negedge
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reset.next = INACTIVE_HIGH
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for i in range(20):
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enable.next = min(1, randrange(3))
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yield clock.negedge
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raise StopSimulation
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@instance
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def monitor():
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print "enable count"
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yield reset.posedge
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while 1:
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yield clock.posedge
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yield delay(1)
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print " %s %s" % (enable, count)
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return clockGen, stimulus, inc_1, monitor
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tb = testbench()
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def main():
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Simulation(tb).run()
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# conversion
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m = 8
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count = Signal(modbv(0)[m:])
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enable = Signal(bool(0))
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clock = Signal(bool(0))
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reset = ResetSignal(0, active=0, async=True)
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inc_inst = Inc(count, enable, clock, reset)
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inc_inst = toVerilog(Inc, count, enable, clock, reset)
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inc_inst = toVHDL(Inc, count, enable, clock, reset)
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if __name__ == '__main__':
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main()
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