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24 lines
404 B
Python
24 lines
404 B
Python
from myhdl import *
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CONTENT = (17, 134, 52, 9)
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def rom(dout, addr, CONTENT):
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""" ROM model """
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@always_comb
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def read():
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dout.next = CONTENT[int(addr)]
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return read
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dout = Signal(intbv(0)[8:])
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addr = Signal(intbv(0)[4:])
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CONTENT = (17, 134, 52, 9)
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def main():
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toVerilog(rom, dout, addr, CONTENT)
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toVHDL(rom, dout, addr, CONTENT)
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if __name__ == '__main__':
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main()
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