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30 lines
283 B
Verilog
30 lines
283 B
Verilog
module tb_ram_1;
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wire [7:0] dout;
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reg [7:0] din;
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reg [6:0] addr;
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reg we;
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reg clk;
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initial begin
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$from_myhdl(
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din,
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addr,
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we,
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clk
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);
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$to_myhdl(
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dout
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);
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end
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ram_1 dut(
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dout,
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din,
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addr,
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we,
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clk
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);
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endmodule
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