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https://github.com/myhdl/myhdl.git
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110 lines
2.7 KiB
Python
110 lines
2.7 KiB
Python
from myhdl import *
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def uart_tx(tx_bit, tx_valid, tx_byte, tx_clk, tx_rst):
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index = Signal(intbv(0, min=0, max=8))
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st = enum('IDLE', 'START', 'DATA')
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state = Signal(st.IDLE)
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@always(tx_clk.posedge, tx_rst.negedge)
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def fsm():
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if tx_rst == 0:
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tx_bit.next = 1
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index.next = 0
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state.next = st.IDLE
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else:
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if state == st.IDLE:
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tx_bit.next = 1
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if tx_valid: # a pulse
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state.next = st.START
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elif state == st.START:
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tx_bit.next = 0
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index.next = 7
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state.next = st.DATA
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elif state == st.DATA:
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tx_bit.next = tx_byte[index]
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if index == 0:
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state.next = st.IDLE
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else:
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index.next = index - 1
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return fsm
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def uart_tx_2(tx_bit, tx_valid, tx_byte, tx_clk, tx_rst):
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index = Signal(intbv(0, min=0, max=8))
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st = enum('IDLE', 'START', 'DATA')
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state = Signal(st.IDLE)
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@always_seq(tx_clk.posedge, reset=tx_rst)
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def fsm():
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if state == st.IDLE:
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tx_bit.next = 1
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if tx_valid: # a pulse
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state.next = st.START
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elif state == st.START:
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tx_bit.next = 0
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index.next = 7
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state.next = st.DATA
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elif state == st.DATA:
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tx_bit.next = tx_byte[index]
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if index == 0:
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state.next = st.IDLE
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else:
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index.next = index - 1
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return fsm
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def tb(uart_tx):
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tx_bit = Signal(bool(1))
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tx_valid = Signal(bool(0))
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tx_byte = Signal(intbv(0)[8:])
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tx_clk = Signal(bool(0))
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# tx_rst = Signal(bool(1))
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tx_rst = ResetSignal(1, active=0, async=True)
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uart_tx_inst = uart_tx(tx_bit, tx_valid, tx_byte, tx_clk, tx_rst)
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# toVerilog(uart_tx, tx_bit, tx_valid, tx_byte, tx_clk, tx_rst)
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@always(delay(10))
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def clk_gen():
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tx_clk.next = not tx_clk
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@instance
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def stimulus():
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tx_rst.next = 1
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yield delay(100)
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tx_rst.next = 0
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yield delay(100)
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tx_rst.next = 1
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yield delay(100)
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for v in (0x00, 0xff, 0x55, 0xaa):
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yield tx_clk.negedge
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tx_byte.next = v
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tx_valid.next = 1
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yield tx_clk.negedge
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tx_valid.next = 0
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yield delay(16 * 20)
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raise StopSimulation
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return clk_gen, stimulus, uart_tx_inst
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sim = Simulation(traceSignals(tb, uart_tx_2))
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sim.run()
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