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52 lines
651 B
Python
52 lines
651 B
Python
from myhdl import *
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def inc_comb(nextCount, count, n):
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@always(count)
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def logic():
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# do nothing here
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pass
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nextCount.driven = "wire"
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__verilog__ =\
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"""
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assign %(nextCount)s = (%(count)s + 1) %% %(n)s;
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"""
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__vhdl__ =\
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"""
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%(nextCount)s <= (%(count)s + 1) mod %(n)s;
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"""
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return logic
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def main():
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m = 8
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n = 2 ** m
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count = Signal(intbv(0)[m:])
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nextCount = Signal(intbv(0)[m:])
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toVerilog(inc_comb, nextCount, count, n)
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toVHDL(inc_comb, nextCount, count, n)
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if __name__ == '__main__':
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main()
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