mirror of
https://github.com/myhdl/myhdl.git
synced 2025-01-24 21:52:56 +08:00
33 lines
378 B
Verilog
33 lines
378 B
Verilog
// File: rom.v
|
|
// Generated by MyHDL 0.7dev
|
|
// Date: Sun Oct 10 21:39:53 2010
|
|
|
|
|
|
`timescale 1ns/10ps
|
|
|
|
module rom (
|
|
dout,
|
|
addr
|
|
);
|
|
// ROM model
|
|
|
|
output [7:0] dout;
|
|
reg [7:0] dout;
|
|
input [3:0] addr;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
always @(addr) begin: ROM_READ
|
|
case (addr)
|
|
0: dout = 17;
|
|
1: dout = 134;
|
|
2: dout = 52;
|
|
default: dout = 9;
|
|
endcase
|
|
end
|
|
|
|
endmodule
|