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40 lines
666 B
VHDL
40 lines
666 B
VHDL
-- File: rom.vhd
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-- Generated by MyHDL 0.7dev
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-- Date: Sun Oct 10 21:39:53 2010
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use std.textio.all;
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use work.pck_myhdl_07dev.all;
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entity rom is
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port (
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dout: out unsigned(7 downto 0);
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addr: in unsigned(3 downto 0)
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);
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end entity rom;
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-- ROM model
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architecture MyHDL of rom is
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begin
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ROM_READ: process (addr) is
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begin
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case to_integer(addr) is
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when 0 => dout <= "00010001";
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when 1 => dout <= "10000110";
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when 2 => dout <= "00110100";
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when others => dout <= "00001001";
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end case;
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end process ROM_READ;
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end architecture MyHDL;
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