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45 lines
747 B
Python
45 lines
747 B
Python
from myhdl import *
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from myhdl.conversion import analyze
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def dff(q, d, clk):
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@always(clk.posedge)
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def logic():
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q.next = d
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return logic
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from random import randrange
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def test_dff():
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q, d, clk = [Signal(bool(0)) for i in range(3)]
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dff_inst = dff(q, d, clk)
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@always(delay(10))
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def clkgen():
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clk.next = not clk
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@always(clk.negedge)
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def stimulus():
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d.next = randrange(2)
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return dff_inst, clkgen, stimulus
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def simulate(timesteps):
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tb = traceSignals(test_dff)
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sim = Simulation(tb)
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sim.run(timesteps)
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simulate(2000)
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def convert():
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q, d, clk = [Signal(bool(0)) for i in range(3)]
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toVerilog(dff, q, d, clk)
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analyze(dff, q, d, clk)
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convert()
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