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39 lines
911 B
Python
39 lines
911 B
Python
import myhdl
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from myhdl import block, always, instance, Signal, ResetSignal, delay, StopSimulation
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from fsm import framer_ctrl, t_state
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ACTIVE_LOW = 0
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@block
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def testbench():
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sof = Signal(bool(0))
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sync_flag = Signal(bool(0))
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clk = Signal(bool(0))
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reset_n = ResetSignal(1, active=ACTIVE_LOW, isasync=True)
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state = Signal(t_state.SEARCH)
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frame_ctrl_0 = framer_ctrl(sof, state, sync_flag, clk, reset_n)
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@always(delay(10))
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def clkgen():
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clk.next = not clk
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@instance
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def stimulus():
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for i in range(3):
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yield clk.negedge
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for n in (12, 8, 8, 4):
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sync_flag.next = 1
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yield clk.negedge
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sync_flag.next = 0
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for i in range(n-1):
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yield clk.negedge
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raise StopSimulation()
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return frame_ctrl_0, clkgen, stimulus
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tb = testbench()
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tb.config_sim(trace=True)
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tb.run_sim()
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