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407 lines
11 KiB
TeX
407 lines
11 KiB
TeX
\chapter{Modeling techniques}
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\section{RTL modeling}
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The present section describes how \myhdl\ supports RTL style modeling
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as is typically used for synthesizable models in Verilog or VHDL. This
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section is included mainly for illustrative purposes, as this modeling
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style is well known and understood.
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\subsection{Combinatorial logic}
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\subsubsection{Template}
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Combinatorial logic is described with a generator function code template as
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follows:
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\begin{verbatim}
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def combinatorialLogic(<arguments>)
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while 1:
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yield <input signal arguments>
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<functional code>
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\end{verbatim}
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The overall code is wrapped in a \code{while 1} statement to keep the
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generator alive. All input signals are clauses in the \code{yield}
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statement, so that the generator resumes whenever one of the inputs
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changes.
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\subsubsection{Example}
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The following is an example of a combinatorial multiplexer:
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\begin{verbatim}
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def mux(z, a, b, sel):
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""" Multiplexer.
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z -- mux output
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a, b -- data inputs
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sel -- control input: select a if asserted, otherwise b
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"""
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while 1:
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yield a, b, sel
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if sel == 1:
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z.next = a
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else:
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z.next = b
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\end{verbatim}
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To verify, let's simulate this logic with some random patterns. The
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\code{random} module in Python's standard library comes in handy for
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such purposes. The function \code{randrange(\var{n})} returns a random
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natural integer smaller than \var{n}. It is used in the test bench
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code to produce random input values:
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\begin{verbatim}
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from random import randrange
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(z, a, b, sel) = [Signal(0) for i in range(4)]
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MUX_1 = mux(z, a, b, sel)
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def test():
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print "z a b sel"
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for i in range(8):
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a.next, b.next, sel.next = randrange(8), randrange(8), randrange(2)
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yield delay(10)
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print "%s %s %s %s" % (z, a, b, sel)
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Simulation(MUX_1, test()).run()
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\end{verbatim}
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Because of the randomness, the simulation output varies between runs
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\footnote{It also possible to have a reproducible random output, by
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explicitly providing a seed value. See the documentation of the
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\code{random} module}. One particular run produced the following
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output:
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\begin{verbatim}
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% python mux.py
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z a b sel
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6 6 1 1
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7 7 1 1
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7 3 7 0
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1 2 1 0
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7 7 5 1
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4 7 4 0
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4 0 4 0
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3 3 5 1
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StopSimulation: No more events
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\end{verbatim}
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\subsection{Sequential logic}
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\subsubsection{Template}
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Sequential RTL models are sensitive to a clock edge. In addition, they
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may be sensitive to a reset signal. We will describe one of the most
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common patterns: a template with a rising clock edge and an
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asynchronous reset signal. Other templates are similar.
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\begin{verbatim}
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def sequentialLogic(<arguments>, clock, ..., reset, ...)
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while 1:
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yield posedge(clock), negedge(reset)
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if reset == <active level>:
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<reset code>
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else:
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<functional code>
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\end{verbatim}
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\subsubsection{Example}
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The following code is a description of an incrementer with enable, and
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an asynchronous power-up reset.
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\begin{verbatim}
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ACTIVE_LOW, INACTIVE_HIGH = 0, 1
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def Inc(count, enable, clock, reset, n):
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""" Incrementer with enable.
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count -- output
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enable -- control input, increment when 1
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clock -- clock input
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reset -- asynchronous reset input
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n -- counter max value
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"""
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while 1:
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yield posedge(clock), negedge(reset)
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if reset == ACTIVE_LOW:
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count.next = 0
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else:
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if enable:
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count.next = (count + 1) % n
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\end{verbatim}
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For the test bench, we will use an independent clock generator, stimulus
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generator, and monitor. After applying enough stimulus patterns, we
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can raise the \code{myhdl.StopSimulation} exception to stop the
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simulation run. The test bench for a small incrementer and a small
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number of patterns is a follows:
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\begin{verbatim}
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count, enable, clock, reset = [Signal(intbv(0)) for i in range(4)]
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INC_1 = Inc(count, enable, clock, reset, n=4)
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def clockGen():
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while 1:
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yield delay(10)
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clock.next = not clock
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def stimulus():
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reset.next = ACTIVE_LOW
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yield negedge(clock)
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reset.next = INACTIVE_HIGH
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for i in range(12):
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enable.next = min(1, randrange(3))
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yield negedge(clock)
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raise StopSimulation
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def monitor():
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print "enable count"
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yield posedge(reset)
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while 1:
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yield posedge(clock)
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yield delay(1)
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print " %s %s" % (enable, count)
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Simulation(clockGen(), stimulus(), monitor(), INC_1).run()
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\end{verbatim}
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The simulation produces the following output:
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\begin{verbatim}
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% python inc.py
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enable count
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0 0
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1 1
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0 1
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1 2
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1 3
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1 0
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0 0
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1 1
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0 1
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0 1
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0 1
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1 2
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StopSimulation
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\end{verbatim}
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\section{High level modeling}
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\begin{quote}
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\em
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This section on high level modeling should become an exciting part of
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the manual, but it doesn't contain a lot of material just yet. One
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reason is that I concentrated on the groundwork first. Moreover,
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though I expect Python to offer some very powerful capabilities in
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this domain, I'm just starting to experiment and learn myself. For
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example, note that so far we haven't used classes (nor meta-classes
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:-)) yet, even though Python has a very powerful object-oriented
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model.
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\end{quote}
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\subsection{Modeling memories with built-in types}
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Python has powerful built-in data types that can be useful to model
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hardware memories. This can be merely a matter of putting an interface
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around some data type operations.
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For example, a \dfn{dictionary} comes in handy to model sparse memory
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structures. (In other languages, this data type is called \dfn{
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associative array}, or \dfn{hash table}.) A sparse memory is one in
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which only a small part of the addresses is used in a particular
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application or simulation. Instead of statically allocating the full
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address space, which can be large, it is better to dynamically
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allocate the needed storage space. This is exactly what a dictionary
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provides. The following is an example of a sparse memory model:
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\begin{verbatim}
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def sparseMemory(dout, din, addr, we, en, clk):
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""" Sparse memory model based on a dictionary.
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Ports:
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dout -- data out
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din -- data in
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addr -- address bus
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we -- write enable: write if 1, read otherwise
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en -- interface enable: enabled if 1
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clk -- clock input
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"""
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memory = {}
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while 1:
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yield posedge(clk)
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if not en:
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continue
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if we:
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memory[addr] = din.val
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else:
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dout.next = memory[addr]
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\end{verbatim}
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Note how we use the \code{val} attribute of the \code{din} signal, as
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we don't want to store the signal object itself, but its current
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value. (In many cases, \myhdl\ can use a signal's value automatically
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when there is no ambiguity: for example, this happens whenever a
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signal is used in expressions. When in doubt, you can always use the
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\code{val} attribute explicitly.)
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As a second example, we will demonstrate how to use a list to model a
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synchronous fifo:
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\begin{verbatim}
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def fifo(dout, din, re, we, empty, full, clk, maxFilling=sys.maxint):
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""" Synchronous fifo model based on a list.
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Ports:
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dout -- data out
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din -- data in
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re -- read enable
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we -- write enable
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empty -- empty indication flag
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full -- full indication flag
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clk -- clock input
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Optional parameter:
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maxFilling -- maximum fifo filling, "infinite" by default
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"""
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memory = []
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while 1:
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yield posedge(clk)
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if we:
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memory.insert(0, din.val)
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if re:
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dout.next = memory.pop()
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empty.next = (len(memory) == 0)
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full.next = (len(memory) == maxFilling)
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\end{verbatim}
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Again, the model is merely a \myhdl\ interface around some operations
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on a list: \function{insert()} to insert entries, \function{pop()} to
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retrieve them, and \function{len()} to get the size of a Python
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object.
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\subsection{Modeling errors using exceptions}
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In the previous section, we used Python data types for modeling. If
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such a type is used inappropriately, Python's run time error system
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will come into play. For example, if we access an address in the
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\function{sparseMemory} model that was not initialized before, we will
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get a traceback similar to the following (some lines omitted for
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clarity):
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\begin{verbatim}
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Traceback (most recent call last):
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...
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File "sparseMemory.py", line 30, in sparseMemory
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dout.next = memory[addr]
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KeyError: 51
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\end{verbatim}
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Similarly, if the \code{fifo} is empty, and we attempt to read from
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it, we get:
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\begin{verbatim}
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Traceback (most recent call last):
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...
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File "fifo.py", line 34, in fifo
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dout.next = memory.pop()
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IndexError: pop from empty list
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\end{verbatim}
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Instead of these low level errors, it may be preferable to define
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errors at the functional level. In Python, this is typically done by
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defining a custom \code{Error} exception at the module level, by
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subclassing the standard \code{Exception} class. This exception is
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then raised explicitly when an error condition occurs.
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For example, we can change function \function{sparseMemory} as follows
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(with the doc string is omitted for brevity):
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\begin{verbatim}
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class Error(Exception):
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pass
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def sparseMemory(dout, din, addr, we, en, clk):
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memory = {}
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while 1:
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yield posedge(clk)
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if not en:
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continue
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if we:
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memory[addr] = din.val
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else:
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try:
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dout.next = memory[addr]
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except KeyError:
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raise Error, "Uninitialized address %s" % hex(addr)
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\end{verbatim}
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This works by catching the low level data type exception, and raising
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the custom exception with an appropriate error message instead. If
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the \function{sparseMemory} function is defined in a module with the
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same name, an access error is now reported as follows:
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\begin{verbatim}
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Traceback (most recent call last):
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...
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File "sparseMemory.py", line 57, in sparseMemory
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raise Error, "Initialize address %s" % hex(addr)
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sparseMemory.Error: Initializes address 0x33
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\end{verbatim}
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Likewise, the \function{fifo} function can be adapted as follows, to
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report underflow and overflow errors:
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\begin{verbatim}
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class Error(Exception):
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pass
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def fifo2(dout, din, re, we, empty, full, clk, maxFilling=sys.maxint):
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memory = []
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while 1:
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yield posedge(clk)
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if we:
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memory.insert(0, din.val)
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if re:
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try:
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dout.next = memory.pop()
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except IndexError:
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raise Error, "Underflow - Read from empty fifo"
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empty.next = (len(memory) == 0)
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full.next = (len(memory) == maxFilling)
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if len(memory) > maxFilling:
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raise Error, "Overflow - Max filling %s exceeded" % maxFilling
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\end{verbatim}
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In this case, the underflow error is detected as before, by catching a
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low level exception on the list data type. On the other hand, the
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overflow error is detected by a regular check on the length of the
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list.
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\begin{quote}
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\em
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Lots of material to be added ...
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\end{quote}
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