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103 lines
1.7 KiB
Python
103 lines
1.7 KiB
Python
from __future__ import generators
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from myhdl import Signal, Simulation, posedge, negedge, delay, StopSimulation
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class Error(Exception):
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pass
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def sparseMemory(dout, din, addr, we, en, clk):
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""" Sparse memory model based on a dictionary.
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Ports:
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dout -- data out
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din -- data in
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addr -- address bus
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we -- write enable: write if 1, read otherwise
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en -- interface enable: enabled if 1
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clk -- clock input
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"""
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memory = {}
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while 1:
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yield posedge(clk)
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if not en:
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continue
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if we:
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memory[addr] = din.val
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else:
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# dout.next = memory[addr]
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try:
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dout.next = memory[addr]
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except KeyError:
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raise Error, "Unitialized address %s" % hex(addr)
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# print memory
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dout, din, addr, we, en, clk = args = [Signal(0) for i in range(6)]
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dut = sparseMemory(*args)
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def clkGen():
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while 1:
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yield delay(10)
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clk.next = not clk
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def read(address):
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yield negedge(clk)
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en.next = 1
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we.next = 0
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addr.next = address
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yield posedge(clk)
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yield delay(1)
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en.next = 0
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we.next = 0
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def write(data, address):
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yield negedge(clk)
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addr.next = address
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din.next = data
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en.next = 1
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we.next = 1
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yield posedge(clk)
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en.next = 0
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we.next = 0
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def test():
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yield write(0x55, 0x55)
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yield write(0x77, 0x77)
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yield write(0x111, 0x111)
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yield read(0x77)
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print hex(dout)
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yield read(0x55)
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print hex(din)
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yield read(0x33)
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sim = Simulation(clkGen(), test(), dut)
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if __name__ == "__main__":
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sim.run()
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