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32c8b7f3e8
- Use myhdl_vpi.so from parent directory - Automatically delete and create work library - Add test target to main makefile
14 lines
382 B
Python
14 lines
382 B
Python
import os
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from myhdl import Cosimulation
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cmd = 'vsim -c -quiet -pli ../myhdl_vpi.so -do cosim.do dut_bin2gray'
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def bin2gray(B, G, width):
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os.system('vlog -quiet +define+width=%s ../../test/verilog/bin2gray.v' % (width))
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os.system('vlog -quiet +define+width=%s ../../test/verilog/dut_bin2gray.v' % (width))
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return Cosimulation(cmd, B=B, G=G)
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