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95 lines
2.1 KiB
VHDL
95 lines
2.1 KiB
VHDL
-- File: FramerCtrl.vhd
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-- Generated by MyHDL 1.0dev
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-- Date: Mon Feb 15 21:03:52 2016
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package pck_FramerCtrl is
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attribute enum_encoding: string;
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type t_enum_t_State_1 is (
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SEARCH,
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CONFIRM,
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SYNC
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);
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attribute enum_encoding of t_enum_t_State_1: type is "001 010 100";
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end package pck_FramerCtrl;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use std.textio.all;
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use work.pck_myhdl_10.all;
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use work.pck_FramerCtrl.all;
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entity FramerCtrl is
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port (
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SOF: out std_logic;
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state: inout t_enum_t_State_1;
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syncFlag: in std_logic;
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clk: in std_logic;
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reset_n: in std_logic
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);
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end entity FramerCtrl;
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-- Framing control FSM.
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--
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-- SOF -- start-of-frame output bit
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-- state -- FramerState output
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-- syncFlag -- sync pattern found indication input
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-- clk -- clock input
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-- reset_n -- active low reset
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architecture MyHDL of FramerCtrl is
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signal index: unsigned(7 downto 0);
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begin
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FRAMERCTRL_FSM: process (clk, reset_n) is
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begin
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if (reset_n = '0') then
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SOF <= '0';
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index <= to_unsigned(0, 8);
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state <= SEARCH;
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elsif rising_edge(clk) then
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index <= ((index + 1) mod 8);
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SOF <= '0';
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case state is
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when SEARCH =>
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index <= to_unsigned(1, 8);
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if bool(syncFlag) then
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state <= CONFIRM;
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end if;
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when CONFIRM =>
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if (index = 0) then
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if bool(syncFlag) then
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state <= SYNC;
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else
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state <= SEARCH;
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end if;
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end if;
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when SYNC =>
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if (index = 0) then
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if (not bool(syncFlag)) then
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state <= SEARCH;
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end if;
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end if;
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SOF <= stdl(signed(resize(index, 9)) = (8 - 1));
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when others =>
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assert False report "End of Simulation" severity Failure;
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end case;
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end if;
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end process FRAMERCTRL_FSM;
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end architecture MyHDL;
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