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73 lines
1.8 KiB
Python
73 lines
1.8 KiB
Python
import os
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path = os.path
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import myhdl
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from myhdl import *
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# SEARCH, CONFIRM, SYNC = range(3)
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ACTIVE_LOW = bool(0)
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FRAME_SIZE = 8
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t_State = enum('SEARCH', 'CONFIRM', 'SYNC', encoding="one_hot")
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@block
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def FramerCtrl(SOF, state, syncFlag, clk, reset_n):
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""" Framing control FSM.
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SOF -- start-of-frame output bit
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state -- FramerState output
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syncFlag -- sync pattern found indication input
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clk -- clock input
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reset_n -- active low reset
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"""
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index = Signal(intbv(0)[8:]) # position in frame
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@always(clk.posedge, reset_n.negedge)
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def FSM():
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if reset_n == ACTIVE_LOW:
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SOF.next = 0
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index.next = 0
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state.next = t_State.SEARCH
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else:
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index.next = (index + 1) % FRAME_SIZE
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SOF.next = 0
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if state == t_State.SEARCH:
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index.next = 1
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if syncFlag:
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state.next = t_State.CONFIRM
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elif state == t_State.CONFIRM:
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if index == 0:
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if syncFlag:
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state.next = t_State.SYNC
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else:
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state.next = t_State.SEARCH
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elif state == t_State.SYNC:
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if index == 0:
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if not syncFlag:
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state.next = t_State.SEARCH
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SOF.next = (index == FRAME_SIZE-1)
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else:
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raise ValueError("Undefined state")
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return FSM
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def main():
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SOF = Signal(bool(0))
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syncFlag = Signal(bool(0))
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clk = Signal(bool(0))
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reset_n = Signal(bool(1))
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state = Signal(t_State.SEARCH)
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toVerilog(FramerCtrl(SOF, state, syncFlag, clk, reset_n))
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toVHDL(FramerCtrl(SOF, state, syncFlag, clk, reset_n))
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if __name__ == '__main__':
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main()
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