mirror of
https://github.com/myhdl/myhdl.git
synced 2024-12-14 07:44:38 +08:00
27 lines
280 B
Verilog
27 lines
280 B
Verilog
module tb_GrayIncReg;
|
|
|
|
wire [7:0] graycnt;
|
|
reg enable;
|
|
reg clock;
|
|
reg reset;
|
|
|
|
initial begin
|
|
$from_myhdl(
|
|
enable,
|
|
clock,
|
|
reset
|
|
);
|
|
$to_myhdl(
|
|
graycnt
|
|
);
|
|
end
|
|
|
|
GrayIncReg dut(
|
|
graycnt,
|
|
enable,
|
|
clock,
|
|
reset
|
|
);
|
|
|
|
endmodule
|