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48 lines
810 B
VHDL
48 lines
810 B
VHDL
-- File: ram.vhd
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-- Generated by MyHDL 0.7dev
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-- Date: Fri Oct 8 21:53:32 2010
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use std.textio.all;
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use work.pck_myhdl_07dev.all;
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entity ram is
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port (
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dout: out unsigned(7 downto 0);
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din: in unsigned(7 downto 0);
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addr: in unsigned(6 downto 0);
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we: in std_logic;
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clk: in std_logic
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);
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end entity ram;
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-- Ram model
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architecture MyHDL of ram is
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type t_array_mem is array(0 to 128-1) of unsigned(7 downto 0);
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signal mem: t_array_mem;
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begin
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RAM_WRITE: process (clk) is
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begin
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if rising_edge(clk) then
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if to_boolean(we) then
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mem(to_integer(addr)) <= din;
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end if;
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end if;
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end process RAM_WRITE;
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dout <= mem(to_integer(addr));
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end architecture MyHDL;
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