mirror of
https://github.com/myhdl/myhdl.git
synced 2025-01-24 21:52:56 +08:00
27 lines
275 B
Verilog
27 lines
275 B
Verilog
// File: inc_comb.v
|
|
// Generated by MyHDL 0.7dev
|
|
// Date: Fri Jul 2 13:23:51 2010
|
|
|
|
|
|
`timescale 1ns/10ps
|
|
|
|
module inc_comb (
|
|
nextCount,
|
|
count
|
|
);
|
|
|
|
|
|
output [7:0] nextCount;
|
|
wire [7:0] nextCount;
|
|
input [7:0] count;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
assign nextCount = (count + 1) % 256;
|
|
|
|
endmodule
|