FPGA/myhdl
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2003-01-23 23:21:31 +00:00
example/arith_lib
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myhdl
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MANIFEST.in
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setup.py
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14 MiB
Languages
Python 86.5%
C 5.8%
Verilog 5.6%
VHDL 1.2%
Shell 0.5%
Other 0.4%