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38 lines
518 B
Verilog
38 lines
518 B
Verilog
// File: bin2gray.v
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// Generated by MyHDL 0.8dev
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// Date: Fri Dec 21 15:02:38 2012
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`timescale 1ns/10ps
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module bin2gray (
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B,
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G
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);
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// Gray encoder.
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//
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// B -- input intbv signal, binary encoded
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// G -- output intbv signal, gray encoded
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// width -- bit width
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input [7:0] B;
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output [7:0] G;
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reg [7:0] G;
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always @(B) begin: BIN2GRAY_LOGIC
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integer i;
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reg [9-1:0] Bext;
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Bext = 9'h0;
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Bext = B;
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for (i=0; i<8; i=i+1) begin
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G[i] = (Bext[(i + 1)] ^ Bext[i]);
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end
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end
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endmodule
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