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33 lines
394 B
Verilog
33 lines
394 B
Verilog
module tb;
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reg [16:0] a;
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reg [4:0] b;
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reg [9:0] c;
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reg clk;
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initial
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begin
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$to_myhdl(c);
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$from_myhdl(a, b);
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end
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always @ (a, b) begin
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c = a + b;
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$display("Verilog: %d c =%d a=%d b=%d", $time, c, a, b);
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end
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initial begin
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clk = 0;
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forever begin
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clk = #50 ~clk;
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end
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end
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endmodule // tb
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