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67 lines
1.8 KiB
Plaintext
67 lines
1.8 KiB
Plaintext
MyHDL Release 0.2
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=================
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INTRODUCTION
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------------
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MyHDL is a Python package for using Python as a hardware description
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language. Popular hardware description languages, like Verilog and
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VHDL, are compiled languages. MyHDL with Python can be viewed as a
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"scripting language" counterpart of such languages. However, Python is
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more accurately described as a very high level language (VHLL). MyHDL
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users have access to the amazing power and elegance of Python for their
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modeling work.
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The key idea behind MyHDL is to use Python generators to model the
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concurrency required in hardware descriptions. As generators are a
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recent Python feature, MyHDL requires Python 2.2.2 or higher.
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MyHDL 0.1 is the initial public release of the package. It can be used
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to experiment with high level modeling, and with verification
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techniques such as unit testing. But the primary goal is to generate
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interest and to solicit feedback.
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In a future release, MyHDL will hopefully be coupled to hardware
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simulators for languages such as Verilog and VHDL. That would turn
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Python into a powerful hardware verification language.
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INSTALLATION
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------------
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If you have superuser power, you can install MyHDL as follows:
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python setup.py install
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This will install the package in the appropriate site-wide Python
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package location.
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Otherwise, you can install it in a personal directory, e.g. as
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follows:
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python setup.py install --home=$HOME
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In this case, be sure to add the appropriate install dir to the
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$PYTHONPATH.
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If necessary, consult the distutils documentation in the standard
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Python library if necessary for more details; or contact me.
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You can test the installation as follows:
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cd test
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python test.py
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DOCUMENTATION
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-------------
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See the doc/ subdirectory.
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EXAMPLES
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--------
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See the example/ subdirectory for examples.
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AUTHOR
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------
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Jan Decaluwe <jan@jandecaluwe.com>
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