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30 lines
312 B
Verilog
30 lines
312 B
Verilog
module tb_FramerCtrl;
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wire SOF;
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wire [2:0] state;
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reg syncFlag;
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reg clk;
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reg reset_n;
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initial begin
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$from_myhdl(
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syncFlag,
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clk,
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reset_n
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);
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$to_myhdl(
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SOF,
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state
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);
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end
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FramerCtrl dut(
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SOF,
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state,
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syncFlag,
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clk,
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reset_n
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);
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endmodule
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