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44 lines
781 B
VHDL
44 lines
781 B
VHDL
-- File: bin2gray.vhd
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-- Generated by MyHDL 0.7
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-- Date: Sun Dec 19 16:52:33 2010
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use std.textio.all;
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use work.pck_myhdl_07.all;
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entity bin2gray is
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port (
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B: in unsigned(7 downto 0);
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G: out unsigned(7 downto 0)
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);
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end entity bin2gray;
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-- Gray encoder.
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--
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-- B -- input intbv signal, binary encoded
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-- G -- output intbv signal, gray encoded
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-- width -- bit width
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architecture MyHDL of bin2gray is
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begin
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BIN2GRAY_LOGIC: process (B) is
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variable Bext: unsigned(8 downto 0);
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begin
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Bext := to_unsigned(0, 9);
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Bext := resize(B, 9);
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for i in 0 to 8-1 loop
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G(i) <= (Bext((i + 1)) xor Bext(i));
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end loop;
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end process BIN2GRAY_LOGIC;
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end architecture MyHDL;
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