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27 lines
272 B
Verilog
27 lines
272 B
Verilog
// File: inc_comb.v
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// Generated by MyHDL 0.7
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// Date: Sun Dec 19 16:52:33 2010
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`timescale 1ns/10ps
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module inc_comb (
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nextCount,
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count
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);
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output [7:0] nextCount;
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wire [7:0] nextCount;
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input [7:0] count;
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assign nextCount = (count + 1) % 256;
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endmodule
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