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41 lines
437 B
Verilog
41 lines
437 B
Verilog
// File: ram_1.v
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// Generated by MyHDL 0.7
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// Date: Sun Dec 19 16:52:33 2010
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`timescale 1ns/10ps
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module ram_1 (
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dout,
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din,
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addr,
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we,
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clk
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);
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// Ram model
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output [7:0] dout;
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wire [7:0] dout;
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input [7:0] din;
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input [6:0] addr;
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input we;
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input clk;
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reg [7:0] mem [0:128-1];
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always @(posedge clk) begin: RAM_1_WRITE
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if (we) begin
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mem[addr] <= din;
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end
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end
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assign dout = mem[addr];
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endmodule
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