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33 lines
375 B
Verilog
33 lines
375 B
Verilog
// File: rom.v
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// Generated by MyHDL 0.7
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// Date: Sun Dec 19 16:52:33 2010
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`timescale 1ns/10ps
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module rom (
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dout,
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addr
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);
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// ROM model
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output [7:0] dout;
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reg [7:0] dout;
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input [3:0] addr;
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always @(addr) begin: ROM_READ
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case (addr)
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0: dout = 17;
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1: dout = 134;
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2: dout = 52;
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default: dout = 9;
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endcase
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end
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endmodule
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