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45 lines
661 B
Verilog
45 lines
661 B
Verilog
// File: Inc.v
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// Generated by MyHDL 0.7dev
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// Date: Fri Jul 2 13:23:50 2010
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`timescale 1ns/10ps
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module Inc (
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count,
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enable,
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clock,
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reset
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);
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// Incrementer with enable.
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//
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// count -- output
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// enable -- control input, increment when 1
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// clock -- clock input
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// reset -- asynchronous reset input
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// n -- counter max value
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output [7:0] count;
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reg [7:0] count;
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input enable;
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input clock;
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input reset;
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always @(posedge clock, negedge reset) begin: INC_INCLOGIC
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if ((reset == 0)) begin
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count <= 0;
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end
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else begin
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if (enable) begin
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count <= ((count + 1) % 256);
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end
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end
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end
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endmodule
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