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65 lines
1.5 KiB
Python
65 lines
1.5 KiB
Python
from myhdl import *
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ACTIVE, INACTIVE = bool(0), bool(1)
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from jc2 import jc2
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from jc2_alt import jc2_alt
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def convert(jc2):
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goLeft, goRight, stop, clk = [Signal(INACTIVE) for i in range(4)]
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q = Signal(intbv(0)[4:])
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toVerilog(jc2, goLeft, goRight, stop, clk, q)
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conversion.analyze(jc2, goLeft, goRight, stop, clk, q)
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convert(jc2)
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convert(jc2_alt)
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def test(jc2):
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goLeft, goRight, stop, clk = [Signal(INACTIVE) for i in range(4)]
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q = Signal(intbv(0)[4:])
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@always(delay(10))
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def clkgen():
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clk.next = not clk
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jc2_inst = jc2(goLeft, goRight, stop, clk, q)
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@instance
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def stimulus():
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for i in range(3):
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yield clk.negedge
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for sig, nrcycles in ((goLeft, 10), (stop, 3), (goRight, 10)):
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sig.next = ACTIVE
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yield clk.negedge
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sig.next = INACTIVE
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for i in range(nrcycles-1):
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yield clk.negedge
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raise StopSimulation
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@instance
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def monitor():
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print "goLeft goRight stop clk q"
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print "-------------------------"
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while True:
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yield clk.negedge
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yield delay(1)
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print "%d %d %d" % (goLeft, goRight, stop) ,
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yield clk.posedge
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print "C",
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yield delay(1)
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print bin(q, 4)
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return clkgen, jc2_inst, stimulus, monitor
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sim = Simulation(test(jc2))
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sim.run()
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print
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print "Alternative design"
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print "------------------"
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sim = Simulation(test(jc2_alt))
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sim.run()
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