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https://github.com/myhdl/myhdl.git
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83 lines
2.1 KiB
Python
83 lines
2.1 KiB
Python
from random import randrange
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from myhdl import *
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from TimeCount import TimeCount
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LOW, HIGH = bool(0), bool(1)
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MAX_COUNT = 6 * 10 * 10
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PERIOD = 10
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def bench():
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""" Unit test for time counter. """
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tens, ones, tenths = [Signal(intbv(0)[4:]) for i in range(3)]
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startstop, reset, clock = [Signal(LOW) for i in range(3)]
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dut = TimeCount(tens, ones, tenths, startstop, reset, clock)
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count = Signal(0)
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counting = Signal(False)
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@always(delay(PERIOD//2))
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def clkgen():
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clock.next = not clock
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## @always(reset.posedge)
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## def clear():
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## counting.next = False
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## count.next = 0
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## @always(startstop.posedge)
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## def go():
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## counting.next = not counting
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@always(startstop.posedge, reset.posedge)
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def action():
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if reset:
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counting.next = False
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count.next = 0
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else:
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counting.next = not counting
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@always(clock.posedge)
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def counter():
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if counting:
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count.next = (count + 1) % MAX_COUNT
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@always(clock.negedge)
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def monitor():
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assert ((tens*100) + (ones*10) + tenths) == count
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@instance
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def stimulus():
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for maxInterval in (100*PERIOD, 2*MAX_COUNT*PERIOD):
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for sig in (reset, startstop,
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reset, startstop, startstop,
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reset, startstop, startstop, startstop,
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reset, startstop, reset, startstop, startstop, startstop):
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yield delay(randrange(10*PERIOD, maxInterval))
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yield clock.negedge # sync to avoid race condition
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sig.next = HIGH
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yield delay(100)
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sig.next = LOW
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raise StopSimulation
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return dut, clkgen, action, counter, monitor, stimulus
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def test_bench():
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sim = Simulation(bench())
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sim.run()
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def convert():
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tens, ones, tenths = [Signal(intbv(0)[4:]) for i in range(3)]
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startstop, reset, clock = [Signal(LOW) for i in range(3)]
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toVerilog(TimeCount, tens, ones, tenths, startstop, reset, clock)
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toVHDL(TimeCount, tens, ones, tenths, startstop, reset, clock)
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convert()
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