FPGA/myhdl
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jand 59a92dff5e Added license headers and module doc strings
2003-01-30 12:09:08 +00:00
example/arith_lib
concat
2003-01-28 23:09:21 +00:00
myhdl
Added license headers and module doc strings
2003-01-30 12:09:08 +00:00
LICENSE.txt
Added license
2003-01-28 10:13:57 +00:00
MANIFEST.in
Put into a project
2003-01-23 23:21:31 +00:00
setup.py
Put into a project
2003-01-23 23:21:31 +00:00
Description
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14 MiB
Languages
Python 86.2%
C 5.9%
Verilog 5.8%
VHDL 1.2%
Shell 0.5%
Other 0.4%