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85 lines
3.1 KiB
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85 lines
3.1 KiB
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********************
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The MyHDL manual
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********************
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.. % \renewcommand{\ttdefault}{cmtt}
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.. % \renewcommand{\sfdefault}{cmss}
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.. % \newcommand{\myhdl}{\protect \mbox{MyHDL}}
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XXX: input{boilerplate} :XXX
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XXX: input{copyright} :XXX
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.. topic:: Abstract
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The goal of the MyHDL project is to empower hardware designers with the elegance
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and simplicity of the Python language.
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MyHDL is a free, open-source (LGPL) package for using Python as a hardware
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description and verification language. Python is a very high level language, and
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hardware designers can use its full power to model and simulate their designs.
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Moreover, MyHDL can convert a design to Verilog. In combination with an external
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synthesis tool, it provides a complete path from Python to a silicon
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implementation.
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*Modeling*
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Python's power and clarity make MyHDL an ideal solution for high level modeling.
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Python is famous for enabling elegant solutions to complex modeling problems.
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Moreover, Python is outstanding for rapid application development and
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experimentation.
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The key idea behind MyHDL is the use of Python generators to model hardware
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concurrency. Generators are best described as resumable functions. In MyHDL,
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generators are used in a specific way so that they become similar to always
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blocks in Verilog or processes in VHDL.
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A hardware module is modeled as a function that returns any number of
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generators. This approach makes it straightforward to support features such as
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arbitrary hierarchy, named port association, arrays of instances, and
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conditional instantiation.
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Furthermore, MyHDL provides classes that implement traditional hardware
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description concepts. It provides a signal class to support communication
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between generators, a class to support bit oriented operations, and a class for
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enumeration types.
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*Simulation and Verification*
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The built-in simulator runs on top of the Python interpreter. It supports
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waveform viewing by tracing signal changes in a VCD file.
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With MyHDL, the Python unit test framework can be used on hardware designs.
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Although unit testing is a popular modern software verification technique, it is
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not yet common in the hardware design world, making it one more area in which
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MyHDL innovates.
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MyHDL can also be used as hardware verification language for VHDL and Verilog
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designs, by co-simulation with traditional HDL simulators.
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*Conversion to Verilog*
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The converter to Verilog works on an instantiated design that has been fully
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elaborated. Consequently, the original design structure can be arbitrarily
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complex.
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The converter automates certain tasks that are tedious or hard in Verilog
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directly. Notable features are the possibility to choose between various FSM
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state encodings based on a single attribute, the mapping of certain high-level
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objects to RAM and ROM descriptions, and the automated handling of signed
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arithmetic issues.
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Contents:
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.. toctree::
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:maxdepth: 2
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background
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intro
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modeling
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unittest
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cosimulation
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conversion
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reference
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