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18 lines
679 B
Plaintext
18 lines
679 B
Plaintext
The examples in this directory are based on VHDL code from the
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"arith_lib" library, Version 1.0, written by Reto Zimmerman, who holds
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the copyright for the original code. The project web page is at
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<http://www.iis.ee.ethz.ch/~zimmi/arith_lib.html>.
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I translated a few modules into myhdl/Python and added testbenches to
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verify and demonstrate myhdl modeling, as well as Python's unit test
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framework. The arith_lib library is useful for these purposes as it
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contains a (simple) behavioral architecture as well as a (sometimes
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complex) structural architecture for each module.
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The testbenches are the files called test_<Name>.py. Run them as
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follows:
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python test_<Name>.py
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