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mirror of https://github.com/myhdl/myhdl.git synced 2025-01-24 21:52:56 +08:00
2005-12-19 10:18:33 +00:00

20 lines
313 B
Python

from myhdl import *
CONTENT = (17, 134, 52, 9)
def rom(dout, addr, CONTENT):
""" ROM model """
@always_comb
def read():
dout.next = CONTENT[int(addr)]
return read
dout = Signal(intbv(0)[8:])
addr = Signal(intbv(0)[4:])
CONTENT = (17, 134, 52, 9)
toVerilog(rom, dout, addr, CONTENT)