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16 lines
217 B
Verilog
16 lines
217 B
Verilog
module dut_dff;
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reg d;
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reg clk;
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reg reset;
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wire q;
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initial begin
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$from_myhdl(d, clk, reset);
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$to_myhdl(q);
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end
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dff dut (.q(q), .d(d), .clk(clk), .reset(reset));
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endmodule // inc
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