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4cad5a171e
They are converted to ternary equivalents in the target HDL. If possible, they are converted to single line assigns. Within a process, this will only work with VHDL-2008.
25 lines
179 B
Plaintext
25 lines
179 B
Plaintext
syntax: glob
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.project
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.pydevproject
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CHANGELOG.txt
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MANIFEST
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*~
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*.pyc
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*.swp
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*.v
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*.vhd
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*_ghdl
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*.o
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*.so
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*.log
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*.cf
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*.vpi
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*.orig
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*.vcd
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*.0
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*.bak
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doc/build
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build/
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dist/
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old_conversion/
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