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FPGA
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myhdl
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myhdl
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cosimulation
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test
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verilog
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jand
7c3bf63a0d
snapshot
2003-05-07 16:52:57 +00:00
..
bin2gray.v
snapshot
2003-05-07 16:52:57 +00:00
dut_bin2gray.v
First working cosimulation unit test
2003-04-24 11:04:01 +00:00
dut_inc.v
inc cosimulation
2003-04-24 19:24:37 +00:00
inc.v
snapshot
2003-05-07 16:52:57 +00:00