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15 lines
224 B
Verilog
15 lines
224 B
Verilog
module dut_bin2gray;
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reg [`width-1:0] B;
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wire [`width-1:0] G;
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initial begin
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$from_myhdl(B);
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$to_myhdl(G);
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end
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bin2gray dut (.B(B), .G(G));
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defparam dut.width = `width;
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endmodule // bin2gray
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