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34 lines
618 B
Verilog
34 lines
618 B
Verilog
module inc(count, enable, clock, reset);
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parameter n = 8;
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input enable;
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input clock;
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input reset;
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output [15:0] count;
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reg [15:0] count;
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initial
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count = 0;
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always @(posedge clock or negedge reset) begin
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$display("Always triggered: count %d", count);
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if (reset == 0) begin
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count <= 0;
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end
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else begin
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if (enable) begin
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count <= (count + 1) % n;
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end
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// $display("count %d", count);
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end
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end // always @ (posedge clock or negedge reset)
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always @ (count) begin
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$display("%d count %d", $time, count);
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end
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endmodule // inc
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