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22 lines
418 B
Python
22 lines
418 B
Python
from myhdl import Signal, ResetSignal, modbv
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from inc import inc
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def convert_inc(hdl):
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"""Convert inc block to Verilog or VHDL."""
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m = 8
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count = Signal(modbv(0)[m:])
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enable = Signal(bool(0))
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clock = Signal(bool(0))
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reset = ResetSignal(0, active=0, isasync=True)
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inc_1 = inc(count, enable, clock, reset)
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inc_1.convert(hdl=hdl)
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convert_inc(hdl='Verilog')
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convert_inc(hdl='VHDL')
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