mirror of
https://github.com/myhdl/myhdl.git
synced 2024-12-14 07:44:38 +08:00
102 lines
3.2 KiB
TeX
102 lines
3.2 KiB
TeX
\documentclass{manual}
|
|
\usepackage{palatino}
|
|
\renewcommand{\ttdefault}{cmtt}
|
|
\renewcommand{\sfdefault}{cmss}
|
|
\newcommand{\myhdl}{\protect \mbox{MyHDL}}
|
|
\usepackage{graphicx}
|
|
|
|
\title{The \myhdl\ manual}
|
|
|
|
\input{boilerplate}
|
|
|
|
\makeindex
|
|
|
|
\begin{document}
|
|
|
|
\maketitle
|
|
|
|
\input{copyright}
|
|
|
|
\begin{abstract}
|
|
|
|
\noindent
|
|
|
|
The goal of the \myhdl{} project is to empower hardware designers with
|
|
the elegance and simplicity of the Python language.
|
|
|
|
\myhdl{} is a free, open-source (LGPL) package for using Python as a
|
|
hardware description and verification language. Python is a very high
|
|
level language, and hardware designers can use its full power to model
|
|
and simulate their designs. Moreover, \myhdl{} can convert a design to
|
|
Verilog. In combination with an external synthesis tool, it provides a
|
|
complete path from Python to a silicon implementation.
|
|
|
|
\emph{Modeling}
|
|
|
|
|
|
Python's power and clarity make \myhdl{} an ideal solution for high level
|
|
modeling. Python is famous for enabling elegant solutions to complex
|
|
modeling problems. Moreover, Python is outstanding for rapid
|
|
application development and experimentation.
|
|
|
|
The key idea behind \myhdl{} is the use of Python generators to model
|
|
hardware concurrency. Generators are best described as resumable
|
|
functions. In \myhdl{}, generators are used in a specific way so that
|
|
they become similar to always blocks in Verilog or processes in VHDL.
|
|
|
|
A hardware module is modeled as a function that returns any number of
|
|
generators. This approach makes it straightforward to support features
|
|
such as arbitrary hierarchy, named port association, arrays of
|
|
instances, and conditional instantiation.
|
|
|
|
Furthermore, \myhdl{} provides classes that implement traditional
|
|
hardware description concepts. It provides a signal class to support
|
|
communication between generators, a class to support bit oriented
|
|
operations, and a class for enumeration types.
|
|
|
|
\emph{Simulation and Verification}
|
|
|
|
The built-in simulator runs on top of the Python interpreter. It
|
|
supports waveform viewing by tracing signal changes in a VCD file.
|
|
|
|
With \myhdl{}, the Python unit test framework can be used on hardware
|
|
designs. Although unit testing is a popular modern software
|
|
verification technique, it is not yet common in the hardware design
|
|
world, making it one more area in which \myhdl{} innovates.
|
|
|
|
\myhdl{} can also be used as hardware verification language for VHDL and
|
|
Verilog designs, by co-simulation with traditional HDL simulators.
|
|
|
|
\emph{Conversion to Verilog}
|
|
|
|
The converter to Verilog works on an instantiated design that has been
|
|
fully elaborated. Consequently, the original design structure can be
|
|
arbitrarily complex.
|
|
|
|
The converter automates certain tasks that are tedious or hard in
|
|
Verilog directly. Notable features are the possibility to choose
|
|
between various FSM state encodings based on a single attribute, the
|
|
mapping of certain high-level objects to RAM and ROM descriptions, and
|
|
the automated handling of signed arithmetic issues.
|
|
|
|
|
|
|
|
\end{abstract}
|
|
|
|
\tableofcontents
|
|
|
|
\input{background.tex}
|
|
\input{intro.tex}
|
|
\input{modeling.tex}
|
|
\input{unittest.tex}
|
|
\input{cosimulation.tex}
|
|
|
|
\chapter{Conversion to Verilog\label{conv}}
|
|
\input{conversion.tex}
|
|
|
|
\input{reference.tex}
|
|
|
|
\input{MyHDL.ind}
|
|
|
|
\end{document}
|