myhdl/olddoc/manual/reference.tex

\chapter{Reference \label{ref}}


\myhdl\ is implemented as a Python package called \code{myhdl}. This
chapter describes the objects that are exported by this package.

\section{Simulation \label{ref-sim}}

\subsection{The \class{Simulation} class \label{ref-simclass}}
\declaremodule{}{myhdl}

\begin{classdesc}{Simulation}{arg \optional{, arg \moreargs}}
Class to construct a new simulation. Each argument should be a
\myhdl\ instance. In \myhdl{}, an instance is recursively defined
as being either a sequence of instances, or a \myhdl\ generator, or a
Cosimulation object. See section~\ref{ref-gen} for the definition of
\myhdl\ generators and their interaction with a
\class{Simulation} object.  See Section~\ref{ref-cosim}
for the \class{Cosimulation} object.  At most one \class{Cosimulation}
object can be passed to a \class{Simulation} constructor.

\end{classdesc}

A \class{Simulation} object has the following method:

\begin{methoddesc}[Simulation]{run}{\optional{duration}}
Run the simulation forever (by default) or for a specified duration.
\end{methoddesc}


\subsection{Simulation support functions\label{ref-simsupport}}
\declaremodule{}{myhdl}

\begin{funcdesc}{now}{}
Returns the current simulation time.
\end{funcdesc}

\begin{excclassdesc}{StopSimulation}{}
Base exception that is caught by the \code{Simulation.run()} method to
stop a simulation.
\end{excclassdesc}


\subsection{Waveform tracing\label{ref-trace}}


\begin{funcdesc}{traceSignals}{func \optional{, *args} \optional{, **kwargs}}
Enables signal tracing to a VCD file for waveform viewing.
\var{func} is a function that returns an instance.
\function{traceSignals()} calls \var{func} under its control
and passes \var{*args} and \var{**kwargs} to the call. In this way, it
finds the hierarchy and the signals to be traced.

The return value is the same as would be returned by the call
\code{func(*args, **kwargs)}.  The top-level instance name and the
basename of the VCD output filename is \code{func.func_name} by
default. If the VCD file exists already, it will be moved to a backup
file by attaching a timestamp to it, before creating the new file.
\end{funcdesc}

The \code{traceSignals} callable has the following attribute:

\begin{memberdesc}[traceSignals]{name}

This attribute is used to overwrite the default top-level instance
name and the basename of the VCD output filename.
\end{memberdesc}

\section{Modeling \label{ref-model}}

\subsection{The \class{Signal} class \label{ref-sig}}
\declaremodule{}{myhdl}

\begin{classdesc}{Signal}{\optional{val=None} \optional{, delay=0}}
This class is used to construct a new signal and to initialize its
value to \var{val}. Optionally, a delay can be specified.
\end{classdesc}

A \class{Signal} object has the following attributes:

\begin{memberdesc}[Signal]{posedge}
Attribute that represents the positive edge of a signal, to be
used in sensitivity lists.
\end{memberdesc}
\begin{memberdesc}[Signal]{negedge}
Attribute that represents the negative edge of a signal, to be
used in sensitivity lists.
\end{memberdesc}

\begin{memberdesc}[Signal]{next}
Read-write attribute that represents the next value of the signal.
\end{memberdesc}

\begin{memberdesc}[Signal]{val}
Read-only attribute that represents the current value of the signal.

This attribute is always available to access the current value;
however in many practical case it will not be needed. Whenever there
is no ambiguity, the Signal object's current value is used
implicitly. In particular, all Python's standard numeric, bit-wise,
logical and comparison operators are implemented on a Signal object by
delegating to its current value. The exception is augmented
assignment. These operators are not implemented as they would break
the rule that the current value should be a read-only attribute. In
addition, when a Signal object is assigned to the \code{next}
attribute of another Signal object, its current value is assigned
instead.
\end{memberdesc}

\begin{memberdesc}[Signal]{min}
Read-only attribute that is the minimum value (inclusive) of a
numeric signal, or \var{None} for no minimum.
\end{memberdesc}
\begin{memberdesc}[Signal]{max}
Read-only attribute that is the maximum value
(exclusive) of a numeric signal, or \var{None} for no 
maximum.
\end{memberdesc}

\begin{memberdesc}[Signal]{driven}
Writable attribute that can be used to indicate that the signal
is supposed to be driven from the MyHDL code, and how it should
be declared in Verilog after conversion. The allowed values
are \code{'reg'} and \code{'wire'}.

This attribute is useful when the Verilog converter cannot
infer automatically whether and how a signal is driven. This
occurs when the signal is driven from user-defined Verilog code.
\end{memberdesc}




\subsection{\myhdl\ generators and trigger objects \label{ref-gen}}
\declaremodule{}{myhdl}

\myhdl\ generators are standard Python generators with specialized
\keyword{yield} statements. In hardware description languages, the equivalent
statements are called 
    \index{sensitivity list}%
\emph{sensitivity lists}. The general format
of \keyword{yield} statements in in \myhdl\ generators is:

\hspace{\leftmargin}\keyword{yield} \var{clause \optional{, clause ...}}

When a generator executes a \keyword{yield} statement, its
execution is suspended at that point. At the same time, each
\var{clause} is a \emph{trigger object} which defines the condition
upon which the generator should be resumed. However, per invocation of a
\keyword{yield} statement, the generator resumes exactly once,
regardless of the number of clauses. This happens on the
first trigger that occurs.

In this section, the trigger objects and their functionality will be
described.

Some MyHDL objects that are described elsewhere can directly be used
as trigger objects. In particular, a signal can be used as
a trigger object. Whenever a signal changes value, the generator
resumes. Likewise, the objects referred to by the signal attributes
\code{posedge} and \code{negedge} are trigger objects. The generator
resumes on the occurrence of a positive or a negative edge on the
signal, respectively. An edge occurs when there is a change from
false to true (positive) or vice versa (negative).
For the full description of the \class{Signal} class and its
attributes, see section~\ref{ref-sig}.

Furthermore, \myhdl\ generators can be used as clauses in \code{yield}
statements. Such a generator is forked, and starts operating
immediately, while the original generator
waits for it to complete. The original generator resumes when the
forked generator returns.


In addition, the following functions return trigger objects:

\begin{funcdesc}{delay}{t}
Return a trigger object that specifies that the generator should
resume after a delay \var{t}.
\end{funcdesc}

\begin{funcdesc}{join}{arg \optional{, arg \moreargs}}
Join a number of trigger objects together and return a joined
trigger object.  The effect is that the joined trigger object will
trigger when \emph{all} of its arguments have triggered.
\end{funcdesc}


Finally, as a special case, the Python \code{None} object can be
present in a \code{yield} statement. It is the do-nothing
trigger object. The generator immediately resumes, as if no
\code{yield} statement were present. This can be useful if the
\code{yield} statement also has generator clauses: those generators
are forked, while the original generator resumes immediately.

\subsection{Decorator functions \label{ref-deco}}
\declaremodule{}{myhdl}

MyHDL defines a number of decorator functions, that make it easier to
create generators from local generator functions.

\begin{funcdesc}{instance}{}
The \function{instance} decorator is the most general decorator.  It
automatically creates a generator by calling the decorated generator function.

It is used as follows:

\begin{verbatim}
def top(...):
    ...
    @instance
    def inst():
        <generator body>
    ...
    return inst, ...
\end{verbatim}

This is equivalent to:

\begin{verbatim}
def top(...):
    ...
    def _gen_func():
        <generator body>
    ...
    inst = _gen_func()
    ...
    return inst, ...
\end{verbatim}

\end{funcdesc}
    

\begin{funcdesc}{always}{arg \optional{, *args}}

The \function{always} decorator is a specialized decorator that targets a widely used
coding pattern. It is used as follows:

\begin{verbatim}
def top(...):
    ...
    @always(event1, event2, ...)
    def inst()
        <body>
    ...
    return inst, ...
\end{verbatim}

This is equivalent to the following:

\begin{verbatim}
def top(...):
    ...
    def _func():
        <body>

    def _gen_func()
        while True:
            yield event1, event2, ... 
            _func()
    ...
    inst = _gen_func()
    ...
    return inst, ...
\end{verbatim}


The argument list of the decorator corresponds to the sensitivity
list. Only signals, edge specifiers, or delay objects are allowed.
The decorated function should be a classic function.


\end{funcdesc}


\begin{funcdesc}{always_comb}{}


The \function{always_comb} decorator is used to describe combinatorial
logic.


\begin{verbatim}
def top(...):
    ...
    @always_comb
    def comb_inst():
        <combinatorial body>
    ...
    return comb_inst, ...
\end{verbatim}


The \function{always_comb} decorator infers the inputs of the combinatorial
logic and the corresponding sensitivity list automatically.
The decorated function should be a classic function.

\end{funcdesc}


\subsection{The \class{intbv} class \label{ref-intbv}}
\declaremodule{}{myhdl}

\begin{classdesc}{intbv}{\optional{val=None} \optional{, min=None} 
\optional{, max=None}}
This class represents \class{int}-like objects with some additional
features that make it suitable for hardware design. The \var{val}
argument can be an \class{int}, a \class{long}, an \class{intbv} or a
bit string (a string with only '0's or '1's). For a bit string
argument, the value is calculated as in \code{int(\var{bitstring},
2)}.  The optional \var{min} and \var{max} arguments can be used to
specify the minimum and maximum value of the \class{intbv} object. As
in standard Python practice for ranges, the minimum value is inclusive
and the maximum value is exclusive.
\end{classdesc}

The minimum and maximum values of an \class{intbv} object
are available as attributes:

\begin{memberdesc}[intbv]{min}
Read-only attribute that is the minimum value (inclusive) of an
\class{intbv}, or \var{None} for no minimum.
\end{memberdesc}
\begin{memberdesc}[intbv]{max}
Read-only attribute that is the maximum value
(exclusive) of an \class{intbv}, or \var{None} for no 
maximum.
\end{memberdesc}

Unlike \class{int} objects, \class{intbv} objects are mutable; this is
also the reason for their existence. Mutability is needed to support
assignment to indexes and slices, as is common in hardware design. For
the same reason, \class{intbv} is not a subclass from \class{int},
even though \class{int} provides most of the desired
functionality. (It is not possible to derive a mutable subtype from
an immutable base type.)

An \class{intbv} object supports the same comparison, numeric,
bitwise, logical, and conversion operations as \class{int} objects. See
\url{http://www.python.org/doc/current/lib/typesnumeric.html} for more
information on such operations. In all binary operations,
\class{intbv} objects can work together with \class{int} objects.
For mixed-type numeric operations, the result type is an \class{int}
or a \class{long}. For mixed-type bitwise operations, the result
type is an \class{intbv}.

In addition, \class{intbv} objects support indexing and slicing
operations:

\begin{tableiii}{clc}{code}{Operation}{Result}{Notes}
  \lineiii{\var{bv}[\var{i}]}
	  {item \var{i} of \var{bv}}
	  {(1)}
  \lineiii{\var{bv}[\var{i}] = \var{x}}  
	  {item \var{i} of \var{bv} is replaced by \var{x}} 
          {(1)}
  \lineiii{\var{bv}[\var{i}:\var{j}]} 
          {slice of \var{bv} from \var{i} downto \var{j}} 
          {(2)(3)}
  \lineiii{\var{bv}[\var{i}:\var{j}] = \var{t}} 
  	  {slice of \var{bv} from \var{i} downto \var{j} is replaced
          by \var{t}} 
          {(2)(4)}
\end{tableiii}

\begin{description}
\item[(1)] Indexing follows the most common hardware design
	  conventions: the lsb bit is the rightmost bit, and it has
	  index 0. This has the following desirable property: if the
	  \class{intbv} value is decomposed as a sum of powers of 2,
	  the bit with index \var{i} corresponds to the term
	  \code{2**i}.

\item[(2)] In contrast to standard Python sequencing conventions,
	  slicing range are downward. This is a consequence of the
	  indexing convention, combined with the common convention
	  that the most significant digits of a number are the
	  leftmost ones. The Python convention of half-open ranges is
	  followed: the bit with the highest index is not
	  included. However, it is the \emph{leftmost} bit in this
	  case. As in standard Python, this takes care of one-off
	  issues in many practical cases: in particular,
	  \code{bv[\var{i}:]} returns \var{i} bits;
	  \code{bv[\var{i}:\var{j}]} has \code{\var{i}-\var{j}}
	  bits. When the low index \var{j} is omitted, it defaults
          to \code{0}. When the high index \var{i} is omitted, it
          means ``all'' higher order bits.

\item[(3)] The object returned from a slicing access operation is always a
	  positive \class{intbv}; higher order bits are implicitly
	  assumed to be zero. The bit width is implicitly stored in
	  the return object, so that it can be used in concatenations
	  and as an iterator. In addition, for a bit width w, the
	  \var{min} and \var{max} attributes are implicitly set to
	  \code{0} and \code{2**w}, respectively.  

\item[(4)] When setting a slice to a value, it is checked whether the
	  slice is wide enough.
\end{description}

In addition, an \class{intbv} object supports the iterator protocol. This
makes it possible to iterate over all its bits, from the high index to
index 0. This is only possible for \class{intbv} objects with a
defined bit width.



\subsection{Miscellaneous modeling support functions\label{ref-model-misc}}
\declaremodule{}{myhdl}

\begin{funcdesc}{bin}{num \optional{, width}}
Returns a bit string representation. If the optional \var{width}
is provided, and if it is larger than the width of the default
representation, the bit string is padded with the sign bit.

This function complements the standard Python conversion functions
\code{hex} and \code{oct}. A binary string representation is often
useful in hardware design.
\end{funcdesc}

\begin{funcdesc}{concat}{base \optional{, arg \moreargs}}
Returns an \class{intbv} object formed by concatenating the arguments.

The following argument types are supported: \class{intbv} objects with
a defined bit width, \class{bool} objects, signals of the previous
objects, and bit strings. All these objects have a defined bit
width. The first argument \var{base} is special as it doesn't need to
have a defined bit width. In addition to the previously mentioned
objects, unsized \class{intbv}, \class{int} and \class{long} objects
are supported, as well as signals of such objects.
\end{funcdesc}

\begin{funcdesc}{downrange}{high \optional{, low=0}}
Generates a downward range list of integers.

This function is modeled after the standard \code{range} function, but
works in the downward direction. The returned interval is half-open,
with the \var{high} index not included. \var{low} is optional and
defaults to zero.  This function is especially useful in conjunction
with the \class{intbv} class, that also works with downward indexing.
\end{funcdesc}

\begin{funcdesc}{enum}{arg \optional{, arg \moreargs} \optional{, encoding='binary'}}
Returns an enumeration type.

The arguments should be string literals that represent the desired
names of the enumeration type attributes.  The returned type should be
assigned to a type name.  For example:
\begin{verbatim}
t_EnumType = enum('ATTR_NAME_1', 'ATTR_NAME_2', ...)
\end{verbatim}
The enumeration type identifiers are available as attributes of
the type name, for example: \code{t_EnumType.ATTR_NAME_1}

The optional keyword argument \var{encoding} specifies the encoding
scheme used in Verilog output. The available encodings are \code{'binary'},
\code{'one_hot'}, and \code{'one_cold'}.
\end{funcdesc}

\begin{funcdesc}{instances}{}
Looks up all \myhdl\ instances in the local name space and returns them
in a list.

\end{funcdesc}


\section{Co-simulation\label{ref-cosim}}
\declaremodule{}{myhdl}

\subsection{\myhdl\ \label{ref-cosim-myhdl}}

\begin{classdesc}{Cosimulation}{exe, **kwargs}
Class to construct a new Cosimulation object. 

The \var{exe} argument is a command string to
execute an HDL simulation. The \var{kwargs} keyword
arguments provide a named association between signals
(regs \& nets) in the HDL simulator and signals in the
\myhdl\ simulator. Each keyword should be a name listed
in a \code{\$to_myhdl} or \code{\$from_myhdl} call in
the HDL code. Each argument should be a \class{Signal}
declared in the \myhdl\ code.

\end{classdesc}

\subsection{Verilog \label{ref-cosim-verilog}}

\begin{funcdesc}{\$to_myhdl}{arg, \optional{, arg \moreargs}}
Task that defines which signals (regs \& nets) should be
read by the \myhdl\ simulator.
This task should be called at the start of the simulation.
\end{funcdesc}

\begin{funcdesc}{\$from_myhdl}{arg, \optional{, arg \moreargs}}
Task that defines which signals should be
driven by the \myhdl\ simulator. In Verilog, only regs
can be specified.
This task should be called at the start of the simulation.
\end{funcdesc}


\subsection{VHDL \label{ref-cosim-vhdl}}

Not implemented yet.

\section{Conversion to Verilog\label{ref-conv}}
\declaremodule{}{myhdl}

\subsection{Conversion \label{ref-conv-conv}}

\begin{funcdesc}{toVerilog}{func \optional{, *args} \optional{, **kwargs}}
Converts a \myhdl\ design instance to equivalent Verilog
code, and also generates a test bench to verify it.
\var{func} is a function that returns an instance.
\function{toVerilog()} calls \var{func} under its control
and passes \var{*args} and \var{**kwargs} to the call.

The return value is the same as would be returned by the call
\code{func(*args, **kwargs)}. It should be assigned
to an instance name.

The top-level instance name and the basename of the Verilog output
filename is \code{func.func_name} by default.

For more information about the restrictions on convertible
\myhdl\ code, see section~\ref{conv-subset} in
Chapter~\ref{conv}.
\end{funcdesc}

The \function{toVerilog} callable has the following attribute:

\begin{memberdesc}[toVerilog]{name}

This attribute is used to overwrite the default top-level instance
name and the basename of the Verilog output filename.

\end{memberdesc}

\subsection{User-defined Verilog code \label{ref-conv-user}}

A user can insert user-defined code in the Verilog output
by using the \code{__verilog__} hook.

\begin{datadesc}{__verilog__}
When defined within a function under elaboration, the
\code{__verilog__} hook variable specifies user-defined code that
should be used instead of converted code for that function.  The
user-defined code should be a Python format string that uses keys to
refer to the variables that should be interpolated in the string. Any
variable in the function context can be referred to.

Note that this hook cannot be used inside generator functions or
decorated local functions, as these are not elaborated.
\end{datadesc}