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53 lines
1.3 KiB
Plaintext
53 lines
1.3 KiB
Plaintext
Release 0.5 Development
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Release 0.4.1 29-Dec-2004
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-------------------------
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* Maintenance release that solves most outstanding issues
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and implements some feature requests.
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See the SourceForge Bug and RFE Trackers for details.
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(Use the group 'MyHDL 0.4' to find the relevant issues.)
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More info can also be found on the mailing list.
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* Added cosimulation support for the cver Verilog simulator.
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Note: the documentation was not modified in this release.
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Release 0.4 4-Feb-2004
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----------------------
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* Conversion to Verilog to provide a path to implementation
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For details, consult the whatsnew04.* documents available
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in various formats under doc/.
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Release 0.3 30-Aug-2003
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-----------------------
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* VCD output for waveform viewing
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* Enumeration types support
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* Inferring the sensitivity list for combinatorial logic
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* Inferring the list of instances
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* Inferring the list of processes
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* Class intbv enhancements
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* Function concat()
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* Python 2.3 support
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For details, consult the whatsnew03.* documents available
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in various formats under doc/.
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Release 0.2 19-May-2003
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-----------------------
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* Added cosimulation support to MyHDL.
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A PLI interface module to the Icarus Verilog simulator is included.
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Release 0.1 7-Mar-2003
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----------------------
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* Initial public release
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