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64 lines
2.7 KiB
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64 lines
2.7 KiB
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Overview
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The goal of the MyHDL project is to empower hardware designers with
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the elegance and simplicity of the Python language.
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MyHDL is a free, open-source package for using Python as a
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hardware description and verification language. Python is a very high
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level language, and hardware designers can use its full power to model
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and simulate their designs. Moreover, MyHDL can convert a design to
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Verilog or VHDL. This provides a path into a traditional design flow.
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*Modeling*
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Python's power and clarity make MyHDL an ideal solution for high level
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modeling. Python is famous for enabling elegant solutions to complex
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modeling problems. Moreover, Python is outstanding for rapid
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application development and experimentation.
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The key idea behind MyHDL is the use of Python generators to model
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hardware concurrency. Generators are best described as resumable
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functions. MyHDL generators are similar to always blocks in Verilog
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and processes in VHDL.
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A hardware module is modeled as a function that returns
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generators. This approach makes it straightforward to support features
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such as arbitrary hierarchy, named port association, arrays of
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instances, and conditional instantiation. Furthermore, MyHDL provides
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classes that implement traditional hardware description concepts. It
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provides a signal class to support communication between generators, a
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class to support bit oriented operations, and a class for enumeration
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types.
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*Simulation and Verification*
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The built-in simulator runs on top of the Python interpreter. It supports
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waveform viewing by tracing signal changes in a VCD file.
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With MyHDL, the Python unit test framework can be used on hardware designs.
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Although unit testing is a popular modern software verification technique, it is
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still uncommon in the hardware design world.
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MyHDL can also be used as hardware verification language for Verilog
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designs, by co-simulation with traditional HDL simulators.
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*Conversion to Verilog and VHDL*
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Subject to some limitations, MyHDL designs can be converted to Verilog
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or VHDL. This provides a path into a traditional design flow,
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including synthesis and implementation. The convertible
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subset is restricted, but much wider than the standard synthesis subset.
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It includes features that can be used for high level modeling and test benches.
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The converter works on an instantiated design that has been
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fully elaborated. Consequently, the original design structure can be
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arbitrarily complex. Moreover, the conversion limitations apply only
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to code inside generators. Outside generators, Python's full power can
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be used without compromising convertibility.
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Finally, the converter automates a number of tasks that are hard in
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Verilog or VHDL directly. A notable feature is the automated handling of
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signed arithmetic issues.
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