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57 lines
1.6 KiB
TeX
57 lines
1.6 KiB
TeX
\documentclass{manual}
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\usepackage{palatino}
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\renewcommand{\ttdefault}{cmtt}
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\renewcommand{\sfdefault}{cmss}
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\newcommand{\myhdl}{\protect \mbox{MyHDL}}
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\title{The \myhdl\ manual}
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\input{boilerplate}
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\begin{document}
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\maketitle
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\input{copyright}
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\begin{abstract}
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\noindent
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\myhdl\ is a Python package for using Python as a hardware description
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language. Popular hardware description languages, like Verilog and
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VHDL, are compiled languages. \myhdl\ with Python can be viewed as a
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"scripting language" counterpart of such languages. However, Python is
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more accurately described as a very high level language
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(VHLL). \myhdl\ users have access to the amazing power and elegance of
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Python for their modeling work.
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The key idea behind \myhdl\ is to use Python generators to model the
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concurrency required in hardware descriptions. As generators are a
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recent Python feature, \myhdl\ requires Python 2.2.2 or higher.
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\myhdl\ can be used to experiment with high level modeling, and with
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verification techniques such as unit testing. The most important
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practical applicaton however, is to use it as a hardware verification
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language by cosimulation with Verilog and VHDL.
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The present release, \myhdl\ 0.2, enables \myhdl\ for
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cosimulation. The \myhdl\ side is designed to work with any simulator
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that has a PLI. For each simulator, an appropriate PLI module in C
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needs to be provided. The release contains such a module for the
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Icarus Verilog simulator.
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\end{abstract}
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\tableofcontents
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\input{background.tex}
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\input{informal.tex}
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\input{modeling.tex}
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\input{unittest.tex}
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\input{cosimulation.tex}
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\input{reference.tex}
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\end{document}
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