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17 lines
291 B
Verilog
17 lines
291 B
Verilog
module dut_inc;
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reg enable;
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reg clock;
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reg reset;
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wire [15:0] count;
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initial begin
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$from_myhdl(enable, clock, reset);
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$to_myhdl(count);
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end
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inc dut (.count(count), .enable(enable), .clock(clock), .reset(reset));
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defparam dut.n= `n;
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endmodule // inc
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