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115 lines
3.6 KiB
ReStructuredText
115 lines
3.6 KiB
ReStructuredText
.. currentmodule:: myhdl
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.. _new09:
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***********************
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What's new in MyHDL 0.9
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***********************
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Python 3 support
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================
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Experimental Python 3 support has been added to MyHDL 0.9.
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This was a major effort to modernize the code. As a result,
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Python 2 and 3 are supported from a single codebase.
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See :doc:`/python3` for more info.
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Interfaces (Conversion of attribute accesses)
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=============================================
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Rationale
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---------
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Complex designs often have many signals that are passed to different levels of
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hierarchy. Typically, many signals logically belong together. This can be
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modelled by an *interface*: an object that has a number of :class:`Signal`
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objects as its attributes. Grouping signals into an interface simplifies the
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code, improves efficiency, and reduces errors.
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The following is an example of an *interface* definition::
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class Complex:
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def __init__(self, min=-2, max=2):
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self.real = Signal(intbv(0, min=min, max=max))
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self.imag = Signal(intbv(0, min=min, max=max))
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Although previous versions supported interfaces for modeling, they were not
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convertible. MyHDL 0.9 now supports conversion of designs that use interfaces.
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The following is an example using the above ``Complex`` interface definition::
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a,b = Complex(-8,8), Complex(-8,8)
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c = Complex(-128,128)
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def complex_multiply(clock, reset, a, b, c):
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@always_seq(clock.posedge, reset=reset)
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def cmult():
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c.real.next = (a.real*b.real) - (a.imag*b.imag)
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c.imag.next = (a.real*b.imag) + (a.imag*b.real)
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return cmult
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Solution
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--------
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The proposed solution is to create unique names for attributes which are used
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by `MyHDL generator`_\s. The converter will create a unique name by using the
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name of the parent and the name of the attribute along with the name of the
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MyHDL module instance. The converter will essentially replace the "." with an
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"_" for each interface element. In essence, interfaces are supported
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using hierarchical name expansion and name mangling.
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Note that the MyHDL convertor supports interfaces, even though
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the target HDLs do not. This is another great example where the
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convertor supports a high-level feature that is not available
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in the target HDLs.
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See also
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--------
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For additional information see the original proposal `mep-107`_.
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.. _mep-107: http://dev.myhdl.org/meps/mep-107.html
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.. _MyHDL generator: http://docs.myhdl.org/en/latest/manual/reference.html#myhdl-generators-and-trigger-objects
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Other noteworthy improvements
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=============================
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``ConcatSignal`` interface
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--------------------------
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The interface of :class:`ConcatSignal` was enhanced. In
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addition to signals, you can now also use constant values
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in the concatenation.
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``std_logic`` type ports
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------------------------
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:func:`toVHDL` has a new attibute ``std_logic_ports``. When
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set, only ``std_logic`` type ports are used in the interface
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of the top-level VHDL module.
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Development flow
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----------------
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The MyHDL development flow has been modernized by moving to git and `github`_
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for version control. In addition, travis has set up so that all pull requests
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are tested automatically, enabling continuous intergration.
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Acknowledgments
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===============
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The Python 3 support effort was coordinated by Keerthan Jaic, who also
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implemented most of if. Convertible interfaces were championed by Chris Felton,
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and implemented by Keerthan Jaic.
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MyHDL development is a collaborative effort, as can be seen on `github`_.
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Thanks to all who contributed with suggestions, issues and pull requests.
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.. _github: https://www.github.com/jandecaluwe/myhdl
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