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130 lines
2.8 KiB
Python
130 lines
2.8 KiB
Python
from __future__ import generators
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import sys
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from myhdl import Signal, Simulation, posedge, negedge, delay, \
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StopSimulation, join
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class Error(Exception):
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pass
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def fifo(dout, din, re, we, empty, full, clk, maxFilling=sys.maxint):
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""" Synchronous fifo model based on a list.
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Ports:
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dout -- data out
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din -- data in
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re -- read enable
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we -- write enable
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empty -- empty indication flag
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full -- full indication flag
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clk -- clock input
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Optional parameter:
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maxFilling -- maximum fifo filling, "infinite" by default
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"""
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memory = []
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while 1:
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yield posedge(clk)
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if we:
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memory.insert(0, din.val)
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if re:
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dout.next = memory.pop()
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filling = len(memory)
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empty.next = (filling == 0)
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full.next = (filling == maxFilling)
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def fifo2(dout, din, re, we, empty, full, clk, maxFilling=sys.maxint):
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""" Synchronous fifo model based on a list.
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Ports:
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dout -- data out
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din -- data in
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re -- read enable
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we -- write enable
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empty -- empty indication flag
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full -- full indication flag
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clk -- clock input
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Optional parameter:
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maxFilling -- maximum fifo filling, "infinite" by default
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"""
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memory = []
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while 1:
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yield posedge(clk)
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if we:
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memory.insert(0, din.val)
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if re:
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try:
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dout.next = memory.pop()
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except IndexError:
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raise Error, "Underflow -- Read from empty fifo"
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filling = len(memory)
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empty.next = (filling == 0)
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full.next = (filling == maxFilling)
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if filling > maxFilling:
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raise Error, "Overflow -- Max filling %s exceeded" % maxFilling
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dout, din, re, we, empty, full, clk = args = [Signal(0) for i in range(7)]
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dut = fifo2(dout, din, re, we, empty, full, clk, maxFilling=3)
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def clkGen():
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while 1:
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yield delay(10)
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clk.next = not clk
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def read():
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yield negedge(clk)
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re.next = 1
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yield posedge(clk)
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yield delay(1)
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re.next = 0
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def write(data):
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yield negedge(clk)
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din.next = data
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we.next = 1
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yield posedge(clk)
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yield delay(1)
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we.next = 0
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def report():
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print "dout: %s empty: %s full: %s" % (hex(dout), empty, full)
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def test():
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yield write(0x55)
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report()
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yield write(0x77)
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report()
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yield write(0x11)
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report()
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yield join(write(0x22), read())
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report()
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yield join(write(0x33), read())
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report()
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yield read()
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report()
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yield read()
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report()
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yield read()
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report()
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yield read()
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report()
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yield read()
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raise StopSimulation
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sim = Simulation(clkGen(), test(), dut)
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if __name__ == "__main__":
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sim.run()
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