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myhdl/example/manual/inc_comb.vhd
2008-11-23 11:36:16 +01:00

30 lines
449 B
VHDL

-- File: inc_comb.vhd
-- Generated by MyHDL 0.6
-- Date: Sun Nov 23 11:34:35 2008
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_06.all;
entity inc_comb is
port (
nextCount: out unsigned(7 downto 0);
count: in unsigned(7 downto 0)
);
end entity inc_comb;
architecture MyHDL of inc_comb is
begin
nextCount <= (count + 1) mod 256;
end architecture MyHDL;