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21 lines
183 B
Verilog
21 lines
183 B
Verilog
module tb_rom;
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wire [7:0] dout;
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reg [3:0] addr;
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initial begin
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$from_myhdl(
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addr
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);
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$to_myhdl(
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dout
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);
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end
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rom dut(
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dout,
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addr
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);
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endmodule
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