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myhdl/scripts/benchmark/convert.py
2015-04-27 16:09:24 -04:00

25 lines
529 B
Python

from __future__ import absolute_import
from myhdl import *
from test_lfsr24 import test_lfsr24
from test_randgen import test_randgen
from test_longdiv import test_longdiv
from test_timer import test_timer
from timer import timer_sig, timer_var
from test_findmax import test_findmax
toVerilog(test_lfsr24)
toVHDL(test_lfsr24)
toVerilog(test_randgen)
toVHDL(test_randgen)
toVerilog(test_longdiv)
toVHDL(test_longdiv)
toVerilog(test_timer, timer_var)
toVHDL(test_timer, timer_var)
toVerilog(test_findmax)
toVHDL(test_findmax)